1) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having the wiring structure formed by burying conductive material in a trench formed through an insulating film above a semiconductor substrate.
2) Description of the Related Art
Development of processing techniques of large scale integrated circuit devices (LSI) makes each semiconductor element increasingly smaller. High density, multi-layers and thinning of wiring lines in LSI are advancing so that stress applied to the wiring lines and the density of current flowing in the wiring lines are increasing more and more. As the density of current flowing in a wiring line increases, electromigration (EM) is likely to occur so that a wiring line may be broken. It is considered that electromigration occurs because electrons transported in a wiring line collide with metal atoms
constituting the wiring line and the metal atoms move or diffuse. As semiconductor elements are made finer, the deterioration of elements by electromigration becomes serious. It is necessary to develop the wiring material and wiring structure which have a high reliability and can suppress electromigration even if current of a high density is flowed.
Copper is wiring material which is more resistant against electromigration than aluminum. However, a copper layer is difficult to be finely worked more than an aluminum layer. A damascene method is practically used as an effective method of forming a wiring line. According to the damascene method, a wiring trench is formed beforehand through an insulating film, copper is buried in this trench, and unnecessary copper is removed to form a wiring line. A dual damascene method is also known by which upper and lower wiring trenches and a via hole connecting the trenches are formed and wiring material is buried in the wiring trenches and via hole at the same time.
High integration and miniaturization of LSI actualize a delay of an electric signal conveyed in a wiring line. In order to reduce a transmission delay of an electric signal, it is important to lower the resistance of wiring material and the dielectric constant of an interlayer insulating film. If low dielectric constant material is used for an interlayer insulating film, it becomes more difficult to form wiring trenches and via holes than using conventional materials of an interlayer insulating film such as undoped silicate glass (silicon oxide, hereinafter abbreviated to USG) and fluorine-doped silicate glass (SiOF, hereinafter abbreviated to FSG).
Known insulating film materials having a low dielectric constant include organic polymer having carbon as its main composition, carbon-containing silicon oxide, and porous materials of these materials. If such low dielectric constant insulating materials are used for an interlayer insulating film, the following problems occur.
First, tight adhesion of an interlayer insulating film to an etching stopper layer, a cap layer, a sacrificial film under chemical mechanical polishing, and a hard mask such as an insulating film and a barrier metal layer is degraded. If stress in terms of thermodynamics is generated during processes such as CMP, heat treatment and bonding, films are likely to be scaled off.
Second, an etching selectivity is lower between an interlayer insulating film and an etching stopper layer of silicon nitride, silicon oxide, silicon carbide or the like and a hard mask. It is therefore difficult to pattern an interlayer insulating film made of low dielectric constant insulating material.
Third, if an interlayer insulating film is made to have a low dielectric constant, a mechanical strength and a thermal stability of the insulating film are degraded. The insulating film may be broken during manufacture processes.
Fourth, if an insulating film is made of porous material, the insulating film is likely to be subjected to secular change and deterioration because of the absorption of moisture in the air, oxidation via fine voids and the like.